• 专利附录
  • 专利说明
  • 权利要求
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    • 专利摘要:
    The integrated circuit includes a heat sink (60) free of electronic components and interposed between a rear face (36) of a low chip (24) and an upper outer face (56) of a housing, the sink having a front face (62) disposed on the rear face of the low electronic chip and a rear face (64), this rear face being between a first and a second plane parallel to the plane of a substrate (10), the first and the second second planes being located, respectively, at 0.15 * H below and 0.15 * H above a back face (32) of a high chip (22, 26), where H is the height of the rear face (32) of the high electronic chip with respect to an inner face (20) of the substrate. The thermal conductivity at 25 ° C of the dissipator is at least two times greater than the thermal conductivity of a thick layer of the housing.
    公开号:FR3023059A1
    申请号:FR1455936
    申请日:2014-06-25
    公开日:2016-01-01
    发明作者:Jamaa Haykel Ben；Laurent Fulbert；Sylvie Menezo；Gilles Poupon
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] INTEGRATED CIRCUIT COMPRISING A HEAT SINK [1] The invention relates to an integrated circuit comprising a heat sink.  The invention also relates to an assembly comprising this integrated circuit as well as a method of manufacturing this integrated circuit.  [2] The evolution of integrated circuits during the last decades has been in the direction of the increase in functionality through the reduction of lithographic dimensions, following the so-called "Moore" law.  For less than a decade, functionalities can be added to the integrated circuit using the possibilities offered by integration according to the vertical dimension, called 3D integration.  This increase in the integration density in the three available dimensions of the integrated circuit has had the direct consequence of increasing the power density, generating an increase in the temperature of the transistors' junctions, and in general of the operating temperature. electronic chips.  [003] Thus, known integrated circuits comprise: a substrate which extends mainly in a plane called "plane of the substrate", this substrate being equipped with electrical connections for electrically connecting the integrated circuit to an external electronic circuit, this substrate having an inner face, 20 - a high electronic chip and a low electronic chip, each of these electronic chips being electrically connected to the electrical connections via this substrate and each electronic chip having a front face facing the inner face of the substrate and a rear face of the opposite side to this front face, the rear face of the high chip being located at a height H 25 above the inner face of the substrate and being further from the inner face of the substrate than the face back of the low chip, - a case formed by a thick layer of material u electrically insulating which encapsulates the electronic chips, this thick layer forming an upper outer face of the housing parallel to the plane of the substrate.  [004] Such integrated circuits are cooled through their upper outer face.  For example, for this purpose, a cooling system is fixed on this upper outer face.  [005] However, the low chip is less well cooled than the high chip because it is further away from the upper outer face.  In these conditions, to avoid excessive heating of the low chip, one solution is to oversize the cooling system of the upper outer face to account for this distance from the low chip.  Another solution is to do nothing and to accommodate the fact that the low chip and less well cooled than the 40 high chip.  The invention aims to overcome this disadvantage by providing an integrated circuit that allows better cooling the low chip without over-size as the cooling system of the integrated circuit.  [7] It therefore relates to an integrated circuit comprising a heat sink 5 devoid of electronic components and interposed between the rear face of the low chip and the upper outer face of the housing, the dissipator having a front face disposed on the face rear of the low chip and a rear face of the opposite side to the front face, this rear face being between a first and a second plane parallel to the plane of the substrate, the first and the second planes being located respectively at 0 , 15 * H below and 0.15 * H above the back of the high chip.  The thermal conductivity at 25 ° C of the dissipator in a direction perpendicular to the plane of the substrate is at least two times greater than the thermal conductivity of the thick layer measured under the same conditions and in the same direction.  [008] Thanks to the presence inside the integrated circuit of the heat sink, which compensates for the difference in height between the rear faces of the high and low chips, a thermal bridge is established between the rear face of the low chip and the upper outer face.  This greatly improves the cooling of the low chip from the upper outer face.  Therefore, it is no longer necessary to over-size the cooling system of the upper outer face to obtain the same cooling of the low chip as in known integrated circuits.  [009] Embodiments of this integrated circuit may have one or more of the following characteristics: the front face of the high electronic chip comprises studs, these studs being directly mechanically and electrically connected to studs with respect to each other; screw so as to transmit electrical signals between the high chip and an electronic circuit outside the high chip via these pads, the rear face of the low chip comprises pads, the front face of the sink comprises pins mechanically fixed on the pads vis-à-vis the rear face of the low chip in the same way that the pads of the high chip are fixed on the pads facing each other; the rear face of the low chip comprises an electrically insulating flat layer 35 for electrically isolating this low electronic chip from the external environment, and the front face of the dissipator is flat and directly in mechanical contact with this flat layer of the rear face. the low chip; the part of the front face of the dissipator directly in mechanical contact with the rear face of the low chip occupies at least 10% or 30% of the area of the orthogonal projection of the rear face of the low chip in the plane of the substrate; the area of the orthogonal projection of the front face of the dissipator on the plane of the substrate is at least 1.1 times greater than the area of the orthogonal projection of the rear face of the low chip on the same plane; heat sink mass is less than 1200 J / Kg / K or 1000 J / Kg / K under normal temperature and pressure conditions; the thickness of the dissipator in a direction perpendicular to the plane of the substrate is greater than 70 μm; the rear face of the high electronic chip and the rear face of the dissipator are flush with the upper outer face of the housing.  The embodiments of this integrated circuit also have the following advantages: - the presence of pads on the heatsink, identical to the pads already used to electrically connect the high chip allows to simplify the fixing of the heatsink on the back side of the low chip because the same method of attachment is used for both the high chip and the sink; a flat front face of the dissipator makes it possible to ensure a larger contact surface with the rear face of the low chip and thus to improve the cooling efficiency of this low electronic chip; having a mechanical contact surface between the front face of the dissipator and the rear face of the low electronic chip, greater than 10% of the area of the orthogonal projection of this rear face makes it possible to increase the cooling efficiency of the low electronic chip; having a surface of the orthogonal projection of the front face of the dissipator strictly greater than the surface of the orthogonal projection of the rear face of the low electronic chip makes it possible to increase the lateral diffusion of the heat and therefore to increase the cooling efficiency of the low chip.  The invention also relates to an assembly comprising: - the integrated circuit above having an upper outer face, and - a radiator or a fluidic cooling system using a coolant 35 for cooling the upper outer face of the circuit integrated, the radiator or the fluidic cooling system being directly disposed on the upper outer face of this integrated circuit.  The invention also relates to a manufacturing method of the integrated circuit above, this method comprising the production of the heat sink, interposed between the rear face of the low chip and the upper outer face of the housing.  The embodiments of this manufacturing method may include the following feature: the realization of the dissipator comprises the electrolytic growth, on the rear face of the low chip, of a layer of a material whose conductivity is at least twice as great as the thermal conductivity of the thick layer when measured under the same conditions and in the same direction, this growth by electrolysis being interrupted at the moment when the thickness of this layer is such that, after the assembly of the high electronic chip on the integrated circuit substrate, the rear face of the dissipator is between a first and a second plane parallel to the plane of the substrate, the first and second planes being located, respectively, at 0.15 * H below and at 0.15 * H above the back side of the high chip; the dissipator is transferred to the rear face of the low chip by bonding or by means of pads; When the heatsink is transferred to the rear face of the low chip and fixed to this low chip by pads, the method comprises a step of filling the space created by the pads with an adhesive containing thermally conductive particles.  The invention will be better understood on reading the description which follows, given solely by way of non-limiting example, and with reference to the drawings in which: - Figure 1 is a schematic vertical sectional illustration an assembly comprising an integrated circuit and a cooling system of this integrated circuit; FIG. 2 is a flowchart of a method of manufacturing the assembly of FIG. 1; FIGS. 3 to 13 are diagrammatic illustrations in vertical section of different steps of the manufacturing method of FIG. 2; FIG. 14 is a diagrammatic illustration in vertical section of a second embodiment of an assembly comprising an integrated circuit and a cooling system of this integrated circuit; Figure 15 is a flowchart of a method of manufacturing the assembly of Figure 14; FIGS. 16 to 27 are diagrammatic illustrations in vertical section of different steps of the method of FIG. 15; FIG. 28 is a schematic illustration of a third embodiment of an assembly comprising an integrated circuit and a cooling system of this integrated circuit.  In these figures, the same references are used to designate the same 5 elements.  In the rest of this description, the features and functions well known to those skilled in the art are not described in detail.  FIG. 1 represents an assembly 2 comprising an integrated circuit 4 and a cooling system 6 of this integrated circuit 4.  The integrated circuit 4 is designed to process signals to fulfill one or more predetermined functions.  The processed signals are electrical or optical signals.  This integrated circuit 4 is electrically connected to an external electronic circuit.  Typically, it is mounted on a printed circuit board or circuit board 8 of the external electronic circuit.  In Figure 1, only a portion of the printed circuit 8 is shown.  For this purpose, the integrated circuit 4 comprises a substrate 10 equipped with electrical connections 12.  The connections 12 electrically and mechanically connect the integrated circuit 4 to the electrical tracks of the printed circuit board 8.  In Figure 1, the tracks of the printed circuit 8 have not been shown.  The substrate 10 extends substantially horizontally parallel to a plane called "plane of the substrate".  The plane of the substrate is parallel to orthogonal directions X and Y.  The vertical direction in the figures is represented by a Z direction perpendicular to the X and Y directions.  Here, the terms such as "above", "below", "upper" and "lower" are defined with respect to the Z direction.  The connections 12 are, for example, fusible balls located on a horizontal outer face 18 of the substrate 10.  The outer face 18 is located on the opposite side to a horizontal inner face.  These fusible balls are soldered on corresponding tracks of the printed circuit board 8.  Such electrical connections are also known as "micro-pillars".  This ball assembly is known by the acronym BGA ("Ball Grid Array").  The beads are, for example, made of a conductive metal such as copper, mixed with a creep material such as tin.  The substrate 10 also comprises electrical tracks electrically connecting the connection pads of the electronic chips to respective connections 12.  To simplify FIG. 1, these electrical tracks of the substrate 10 have not been shown.  Typically, the substrate 10 is made of a hard material whose hardness is for example greater than or equal to that of silicon.  Here, the substrate 10 is made of silicon.  The thickness of the substrate 10 is typically greater than 100 μm or 300 μm.  The integrated circuit 4 is a three-dimensional integrated circuit, that is to say that inside the housing of this integrated circuit, there are at least two electronic chips stacked one above the other. the other in the vertical direction Z.  By way of illustration, the integrated circuit 4 comprises three electronic chips 22, 24 and 26.  In general, an electronic chip has many active or passive electrical components to perform a predetermined function.  An active electrical component is defined as an electronic component that increases the power of a signal, such as voltage or current, or both.  Extra power is recovered through a power supply.  These are typically components made from semiconductors such as transistors or thyristors.  It can also be an optoelectronic component.  Conversely, a passive electronic component is defined as not making it possible to increase the power of a signal.  It is typically a resistor, a capacitor, an inductor or a coil or a diode or any assembly of these components.  An electronic chip is also known by the English term "die".  It includes a front face facing the substrate 10 and, on the opposite side, a rear face.  These front and rear faces extend substantially parallel to the plane of the substrate.  Typically, the active or passive components of the electronic chip are made in one of the front or rear faces or inside this chip.  For example, in this embodiment, the active or passive components are made in the front face of each chip.  The front and rear faces are each formed by a passivation layer possibly traversed by pads of electrical connections.  The passivation layer electrically isolates the chip from the external environment.  The connection pads electrically and mechanically connect the chip to other chips of the integrated circuit 4 or to the substrate 10.  These pads allow each chip to exchange electrical signals with these other chips or with the substrate 10.  Here, the front and rear faces of the chips 22, 24 and 26 bear, respectively, the numerals 30 and 32, 34 and 36, 38 and 40.  More specifically, the front faces 30 and 34 are directly mechanically and electrically connected to the inner face 20 of the substrate 10 by electrical connections 42.  For example, these electrical connections are also made by means of microballs 35 fusible or micro-pillars forming a set BGA.  The front face 38 of the chip 26 is mechanically and electrically directly connected to the rear face 36 of the chip 24.  For this purpose, in this embodiment, the front face 38 and the rear face 36 each comprise pads 44 vis-à-vis each other.  In FIG. 1, the pads 44 40 belonging to the face 38 of the facing pads belonging to the face 36 can not be distinguished.  These studs 44 are of micrometric size and also known as "micro-pillars".  More specifically, these faces each comprise a flat bottom from which the studs 44 project vertically.  Typically, the horizontal section of each stud 44 is constant over the essential of its height.  The diameter of this horizontal section is generally between 0.1 μm and 100 μm, and most often between 5 μm and 30 μm or between 5 μm and 20 μm.  Here, the diameter of the pads 44 is 20 μm and the spacing between the pads 44 is 50 μm.  When the horizontal section of the pads 44 is not circular, by "diameter" designates the hydraulic diameter considering that the entire perimeter of the horizontal section is wet.  The height of each pad 44, measured from the flat bottom, is generally between 1 μm and 200 μm and, most often, between 10 μm and 100 μm.  These pads 44 are made of electrically conductive material.  Here, it is considered that a material is electrically conductive if its electrical conductivity at 20 ° C is greater than 1 S / m and, preferably, greater than 105 or 107 S / m.  For example, the pads 44 are made of copper.  Other details on the pads 44 are given with regard to the manufacturing process of the assembly 2.  The rear faces 32 and 40 are located at the same height, that is to say in the same horizontal plane 46.  The rear face 36 is located at a height much lower than that of the rear faces 32 and 40.  For example, the back face 36 is located at more than 50 μm or 100 μm below the plane 46.  Here, the chips 22 and 26 comprise, for example, MOS transistors ("Metal Oxide Semiconductor") and are able to process electrical signals to perform arithmetic and logic calculations.  The chips 22 and 26 therefore constitute heat sources when they operate to perform calculations from the electrical signals provided.  In the remainder of this description, a heat source designates a zone of the integrated circuit dissipating a pfd exceeding 1 W / cm 2.  For example, here the pfd dissipated by a heat source is 5 W / cm 2 or 10 W / cm 2 or 50 W / cm 2.  The chip 24 comprises an optoelectronic component 48 such as a generator 30 of a laser beam.  For example, the component 48 is used to convert electrical signals into optical signals transmitted outside the integrated circuit 4.  For this purpose, the integrated circuit 4 also comprises a connector 50 for connecting an optical cable to the chip 24.  Component 48 also forms a source of heat when it operates.  Indeed, a substantial portion of the electrical energy received by this component 48 for generating the laser beam is dissipated as heat.  The integrated circuit 4 comprises a housing formed by a thick layer 54.  The layer 54 protects the chips 22, 24 and 26 and the face 20 of the substrate against mechanical and chemical attack from the external environment of the integrated circuit 4.  For this purpose, it covers and directly coats: - the face 20 of the substrate 10, - the vertical faces of the chips 22, 24 and 26, and - in this embodiment, a part of the rear face 36 of the chip 24.  The layer 54 also has a horizontal outer top surface 56 facing away from the substrate 10.  Here, the outer face 56 is the face of the integrated circuit 4 on which is mounted directly the cooling system 6.  To improve the heat exchange between the chips 22, 26 and the system 6, the plane 46 containing the faces 32 and 40 is located at least 50 μm and, typically, less than 10 μm under the outer face 56.  Preferably, as in this embodiment, the faces 32 and 40 are flush with the outer face 56.  Here, the outer face 56 is thus contained in the plane 46.  More specifically, the layer 54 protects the chips 22, 24 and 26 against moisture and mechanical shocks.  For this purpose, with regard to humidity, the layer 54 satisfies the tightness test called "wet heat".  Such a leak test is for example defined in the GEDEC standards.  This standard defines in particular the following test: 1) characterization of the integrated circuit under standard conditions, 2) placing the integrated circuit hundreds of hours, typically more than 500 hours, at 85 ° C with a humidity of 85%, then 20 3 ) characterize the operation of the integrated circuit under standard condition.  If the values recorded in points 1) and 3) above are equal to a margin of error predefined by the GEDEC standard, then the layer 54 is said waterproof.  To protect the electronic chips against shocks, the thick layer is made of a material which makes it possible to distribute and lower the mechanical stresses between the chips 22, 24 and the substrate 10.  For example, for this purpose, the Young's modulus at 25 ° C. of the layer 54 is chosen strictly lower than that of the chips 22 and 24.  Typically, the Young's modulus of chips 22, 24 is substantially equal to the Young's modulus of silicon.  The Young's modulus of layer 54 is then selected generally less than 100 GPa or 20 GPa at 25 ° C.  Layer 54 is also electrically insulating to electrically isolate chips 22, 24 and 26 from the outside environment.  Here, it is considered that a layer is electrically insulating if its conductivity at 20 ° C is less than 10 -4 S / m and, preferably, less than 10-7 or 1040 S / m.  To achieve these results, generally, the layer 54 comprises a certain volume of polymer which varies from 5% to 100% of the total volume of the layer 54.  The volume of polymer is often greater than 50% of the total volume.  Typically, the polymer is uniformly distributed in layer 54.  It may be for example an epoxy resin.  In addition, generally, the layer 54 has a low thermal conductivity, that is to say a thermal conductivity at 20 ° C of less than 50 W. m-1. K-1 and, typically, less than 15 W. m1. Ki or 5 or 2 W. m-1. K-1.  Given the low thermal conductivity of the thick film 54 and the fact that the rear face 36 is remote, typically more than 50 μm, from the outer face 56, it is difficult to effectively cool the chip 24 to the outer surface. 6 cooling system help.  To avoid this problem, the integrated circuit 4 comprises a heat sink 60 interposed between the rear face 36 and the outer face 56.  The dissipator 60 is a thermally good conductive material block 10 whose function is to establish a thermal bridge between the zone of the rear face 36 which heats up the most and the outer face 56.  Here, the zone of the rear face 36 which heats up the most is located vertically optoelectronic component 48.  Thereafter, a good thermal conductor means a material or a block of material whose thermal conductivity at 25 ° C, in the vertical direction, is at least two times greater than the thermal conductivity of the thick layer 54 measured in the same conditions and in the same direction.  Preferably, the thermal conductivity of the dissipator 60 in the vertical direction is at least four, ten or fifty times greater than the thermal conductivity of the layer 54 in the same direction.  Thus, typically, the thermal conductivity at 25 ° C of block 60 is greater than 10 W / m / K or 100 W / m / K and, preferably, greater than 200 W / m / K or 300 W / m / K.  The heatsink 60 does not perform any other function than that of heat sink.  As a result, it lacks an active or passive electronic component.  In addition, it is preferably electrically isolated from the electronic chips and the substrate 10 or only electrically connected to the ground of the integrated circuit 4.  The dissipator 60 has a front face 62 vis-à-vis the rear face 36 and a rear face 64 located on the opposite side to this front face 62.  These faces 62 and 64 extend mainly horizontally.  The area of the orthogonal projection 30 of the front face 62 in a horizontal plane is greater than 10% and, preferably, greater than 20% or 40% of the area of the orthogonal projection of the rear face 36 in this same plane.  The face 62 is directly in contact with the rear face 36.  Here, the face 62 has a horizontal flat bottom and pads 66 protruding vertically downwardly from this bottom.  These pads 66 are designed to be mechanically and thermally connected to pads 44 of the rear face 36 vis-à-vis.  These pads 66 are structurally identical to the pads 44, except as regards their height which may be different from that of the pads 44.  Here, the pads 66 are made of the same material as the pads 44, because the copper is a good thermal conductor material.  However, other materials good thermal conductors are possible for the pads 66.  In this embodiment, only the end of the pads 66 is in direct mechanical contact with the rear face 36.  The number and the dimensions of the pads 66 are determined so that the surface of the front face 62 in direct mechanical contact with the rear face 36 is at least greater than 10 or 20% and preferably greater than 35% or 45%, the surface of the orthogonal projection of this front face 62 in a horizontal plane.  Here, the surface of the front face 62 directly mechanically in contact with the rear face 36 is between 30% and 50% of the area of the orthogonal projection of the front face 62 on a horizontal plane.  Here, the pads 66 are 20 μm in diameter and are spaced from each other with a pitch of 50 μm.  The rear face 64 is flat and horizontal.  This rear face is located at the same level as the rear faces 32 and 40 of chips 22 and 26 said high.  Here, a chip is said to be "high" if it has the rearmost face furthest from the inner face 10 of the substrate.  With the exception of the high chip or chips, the other chips of the integrated circuit are called "low".  Thus, here, the chip 24 is a low chip because it has a rear face 68 closer to the inner face 10 than the faces 32 or 40.  By "located at the same level" is meant that face 64 is between first and second horizontal planes located, respectively, below and above the rear face of the high chip.  The height of the foreground is equal to the height H of the rear face of the high chip minus 0.15 * H or less 0.10 * H or less 0.05 * H (the symbol "*" means "multiplied by" ).  The height of the second plane is equal to the height H plus 0.15 * H or more 0.10 * H or more 0.05 * H.  The height H is the height of the rear face of the high chip with respect to the inner face 20 of the substrate 10.  The height H is measured vertically.  For example, the height of the rear face 64 is equal to the height of the rear face 32 or 40 to plus or minus 10 pm or plus or minus 5 pm.  By way of illustration, here the height H is equal to or greater than 100 μm.  In addition, advantageously, the rear face 64 is between the plane 46 and another horizontal plane located less than 50 pm or 10 pm under the plane 46.  Preferably, as shown here, the rear face 64 is flush with the outer face 56.  Here, it is located in the plane 46.  The front 62 and rear 64 faces are mechanically connected to each other by vertical faces.  The height of the dissipator 60 measured between the flat bottom and the rear face 64 is typically greater than 10 μm or 100 μm, and generally less than 700 μm.  Here, this height is between 100 pm and 300 pm.  To ensure a rapid dissipation of heat to the cooling system 6, the heatsink 60 must quickly conduct the heat and not too much 40 to store it.  The dissipator 60 therefore does not include phase change material or PCM ("Phase Change Material").  For this purpose, the material in which the body of the dissipator is made represents a specific heat capacity, measured under normal conditions of temperature and pressure of less than 1250 J / Kg / K or less than 1000 J / Kg / K or still below 750 J / Kg / K.  The body of the dissipator 60 is the part situated between the flat bottom of the front face 62 and the rear face 64, that is to say the dissipator without the pads 66.  Here, this body is a thermally homogeneous block in a single material.  The body of the dissipator 60 is not necessarily made of the same material as the pads 66.  Here, it is made of silicon or aluminum.  In order to improve the heat conduction between the front face 62 and the rear face 36, the interstices between the pads 44 and 66 are filled with an adhesive 68 made of a good thermal conductive bonding material.  For example, this bonding material comprises a polymer material mixed with particles of thermally conductive material.  For example, the particles are metal particles such as copper or silver particles.  The particles may also be graphene or graphite particles or other materials such as silicon oxide.  These particles are generally in the form of nanoparticles, that is to say particles whose longest length is less than 1 μm and, typically, less than 100 nm or 10 nm.  [0050] The cooling system 6 comprises a radiator 70.  This radiator 70 has a planar face directly in mechanical and thermal contact with the outer face 56.  This flat face covers all the rear faces 32, 40 and 62.  On the opposite side, the radiator 70 has a flat bottom from which fins 72 protrude to increase the contact surface between this radiator 70 and the external environment, and thus promote conductive heat exchange with this external medium.  The operation of the integrated circuit 4 is as follows.  When the component 48 operates, it generates heat.  This heat is diffused preferentially by conduction of the rear face 36 towards the front face 62 of the dissipator 60, then from the front face 62 to the rear face 64 and, finally, from the rear face 64 towards the radiator 70.  The presence of the dissipator 60 accelerates the heat exchange between the rear face 36 and the radiator 70.  This makes it possible to maintain the rear face 36 at a temperature T1 much lower than that which would be observed in the absence of the dissipator 60.  Simulations have shown that in normal operation, the temperature T1 is at least 10 ° C or 20 ° C, or even less than at least 50 ° C with respect to the temperature that would be observed under the same conditions and in an identical integrated circuit but devoid of the dissipator 60.  A method of manufacturing assembly 2 will now be described with reference to FIGS. 2 to 13.  The process begins with the collective manufacture of the dissipator 60.  More specifically, during a step 90 (FIG. 3), a silicon wafer 92 is supplied and then oxidized so as to form a layer of silicon oxide 94 over this plate.  In a step 96 (FIG. 4), a tie layer and a nucleation layer are deposited on the layer 94.  In FIG. 4, these layers are represented by the same layer 98.  The bonding layer is for example titanium or titanium nitride and the nucleation layer is here copper.  In a step 100 (Figure 5), a layer 102 of resin is deposited on the layer 98 and structured by photolithography to develop locations 104 where the layer 98 is directly exposed to the outside.  During a step 106 (FIG. 6), copper electrodes are grown by electrolysis from the bottom of the locations 104.  The free end of each copper pad is then covered with a finishing layer 110 in a creep material.  Here, the creep material is a SnAg alloy.  The studs 66 are thus obtained.
    [0002] In the figures, the number of pads 66 shown has been limited to simplify the graphic illustrations. In a step 112 (Figure 7), it proceeds to a shaping heat treatment of the SnAg alloy. This makes it possible to prevent this metal alloy from flowing on the vertical edges of the pads 66 during the subsequent creep step. In a step 114 (Fig. 8), the resin layer 102 is removed, for example, by dissolution. In a step 116 (Figure 9), the plate 92 of silicon is cut to separate mechanically from each other the different heatsinks 60 collectively manufactured so far. In a step 118 (FIG. 10), the dissipator 60 and the chip 26 are assembled and transferred to the rear face 36 of the chip 24. For this purpose, the chip 26 and the dissipator 60 are brought and positioned on the rear face 36 using a same process known as "pick and place". During step 118, this step is performed on a plate containing several chips 24 so as to stack the chip 26 and the dissipator 60 collectively on several chips 24. To stiffen the plate containing the different chips 24, a temporary substrate or temporary handle 120 is glued to this plate. In Figure 10, only a chip 24 of this plate is shown. In a step 122 (FIG. 11), a heat treatment is applied to flow the SnAg alloys. This allows the pads 44 and 66 to be mechanically welded together. This mechanical connection also makes it possible to obtain an electrical and thermal connection between these pads. The heat treatment is applied simultaneously to the pads 44 of the chips 24 and 26 and to the pads 66 of the dissipator 60. Thus, the mechanical attachment of the chip 26 and the dissipator 60 on the rear face 36 40 of the chip 24 is made in a single surgery. In a step 124 (Figure 12), the glue 68 is dispersed between the pads 44 and 66 to completely fill the interstices between these pads. This improves the mechanical strength of the dissipator 60 on the rear face 36 of the chip 24. This also improves the heat connection of the dissipator 60 on the rear face 36. Optionally, as illustrated here, the same glue 68 is also dispersed between the chips 24 and 26. [0063] During a step 128 (FIG. 13), the temporary handle 120 is peeled off, then the plate containing the different chips 24 is cut so as to mechanically isolate from each other subassemblies each comprising Chip 24 on which are fixed the chip 26 and the dissipator 60. Then, during a step 130, a subassembly obtained in step 128 is welded to the substrate 10. At this step 130, the chip 22 is also welded to the substrate 10. The positioning of the subassembly and the positioning of the chip 22 on the substrate 10 during this step 130 are, for example, carried out using the same method "Pick and pla this ". In a step 132, the thick layer 54 is molded on the substrate 10 and the chips 22, 24 and 26 and the dissipator 60, so as to form the housing of the integrated circuit 4. Finally, when a step 134, the cooling system 6 is directly fixed on the outer face 56 of the integrated circuit 4. [0067] FIG. 14 represents an assembly 146 identical to the assembly 2, except that the integrated circuit 4 is replaced by an integrated circuit 148. The integrated circuit 148 is identical to the integrated circuit 4, except that the heatsink 60 is replaced by a heatsink 150. The heatsink 150 differs from the heatsink 60 only: in that the front face 62 is replaced by a front face 152 plane, and - in that the body of the dissipator 150 is made of copper and not of silicon. In this embodiment, the front face 152 is devoid of stud 66. It is directly in mechanical contact with the rear face 36 of the chip 24 over its entire surface. For this purpose, the front face 152 bears on a flat area of the rear face 36, that is to say an area of the rear face 36 without stud 44. [0069] A method of manufacturing the The assembly 146 will now be described with reference to FIGS. 15 to 27. [0070] In a step 160 (FIG. 16), a plate on which several electronic chips 24 have been collectively manufactured is provided. This plate is glued on a temporary handle 162. To simplify the figures, only a portion of this plate containing only a single chip 24 is shown. In a step 164 (Figure 17), the manufacture of the chip 24 is completed by the deposition of a passivation layer 166 to form the rear face 36 of the chip 40 24. The layer 166 is made in an electrically insulating material and covers the entire back of the chip 24, except the locations where pads 44 must be made. In a step 168 (Figure 18), a tie layer and a nucleation layer are deposited. This step is for example identical to step 96 of the method of FIG. 2. In the figures, these two layers are represented by a single layer 170. [0073] In a step 172 (FIG. Resin 174 is deposited and then photolithographically structured to form locations 176. At the bottom of each location 176, a portion of the layer 170 is directly exposed to the exterior. In a step 178 (Figure 20), the locations 176 are filled, by electrolysis, with copper, then surmounted by a creep layer SnAg to form the pads 44 of the rear face 36 of the chip 24. [0075] In a step 180 (FIG. 21), the resin layer 176 is removed, for example, by dissolution. In a step 182 (FIG. 22), a new resin layer 184 is deposited, then structured by photolithography to provide a location 186 above the component 48. The location 186 makes it possible to expose to the only part of the layer 170 located directly above the component 48. [0077] In a step 188 (FIG. 23), a layer of copper is deposited and grown electrolytically. only inside the location 186. The growth of this copper layer is stopped when the thickness of this layer is such that the rear face 64 is at the same height as the rear faces 32 and 40 of the electronic chips 22 and 26 after assembling the chips 22, 24, 26 and the dissipator 150 on the substrate 10. At the end of step 188, the manufacture of the dissipator 150 and its attachment to the chip 24 are completed. In a step 190 (Figure 24), the resin layer 184 is removed, for example, by dissolution. In a step 192 (Figure 25), the layer 170 between the pads 44 is removed by etching. In a step 194 (Figure 26), a heat treatment, identical to that of step 112 is applied to shape the pads 44. In a step 196 (Figure 27), the electronic chip 26 is assembled on the rear face 36. This step 196 is carried out in the same manner as that described with reference to the steps 118, 122 and 124 of the method of FIG. 2. However, it will be noted that in FIG. this embodiment, the glue 68 is only dispersed between the pads 44 located under the chip 26. [0082] Then, steps 200, 202, 204 and 206 are identical, respectively, to the steps 128, 130, 132 and 134 of the method of FIG. 2. FIG. 28 represents an assembly 216 identical to the assembly 2, except that the integrated circuit 4 is replaced by an integrated circuit 218. This integrated circuit 218 is distinguished from the integrated circuit 4 by the fact that the chip 24 and the dissipator 60 are replaced, respectively, by an electronic chip 220 and a heatsink 222. The heatsink 222 is identical to the heatsink 150 except that it is wider than the electronic chip 220. Therefore, its front face extends, in a horizontal direction, and on each side, beyond the rear face of the chip 220. Such an arrangement of the heat sink 222 further promotes the dissipation of the heat generated by the chip 220 on the vertical sides of the integrated circuit 218. In this embodiment, for example, the heatsink 222 has a flat front face and no stud which is directly adhered to the rear face of the electronic chip 220. In this case, the rear face of the electronic chip 220 is also flat and horizontal. The adhesive used to make this bonding is, for example, the adhesive 68. Typically, the surface of the front face of the dissipator 222 is at least 1.1 times and, preferably 1.5 times or twice, greater than the surface of the rear face of the chip 220. [0084] Many other embodiments are possible. For example, alternatively, the chip 26 is omitted. In this case, the height of the dissipator 60 is adjusted so that its rear face is at the height of the rear face 32 of the chip 22. In another embodiment, the chip 22 is omitted. What has been described above applies to all integrated circuits comprising several electronic chips whose rear faces are located at different heights. In the case where the integrated circuit comprises several chips each having a rear face at a height greater than that of the rear face 36, preferably the rear face 64 of the dissipator is located at the rear face of the high chip. . Note also that the chip 24 can be replaced by another chip devoid of opto-electronic components. The rear face of an electronic chip or dissipator is not necessarily flat and horizontal. For example, it may have roughness.
    [0003] In this case, the plane of the rear face used to measure the height H is the horizontal plane which minimizes the root mean square of the vertical deviations between this plane and each point of this rear face. The integrated circuit may also contain several heatsinks such as the heatsinks 60, 150 or 222. For example, several heatsinks are arranged on different respective zones of the same rear face of an electronic chip. It is also possible to have several heatsinks on respective rear faces of several different electronic chips. The electrical connections 12 can take other forms. For example, alternatively, the electrical connections 12 are pins projecting beyond the housing of the integrated circuit 4. [0089] The electronic components of a chip are not only made on the front face of this chip. For example, alternatively, the electronic components are also made on the back side or enclosed within the electronic chip. The body of the dissipator may be made of other thermally good conductor materials, including in the case of the dissipator 60. For example, this body is made of copper or aluminum. The heatsink body does not necessarily consist of a single layer between its front and rear faces. Thus, alternatively, the body consists of a stack of several layers of thermally good conducting materials, directly deposited on each other in the vertical direction. For example, this stack comprises at least one silicon layer and at least one silicon carbide layer. In another embodiment, this stack comprises at least one layer of graphite. Alternatively, one of the layers may also be a graphene layer to increase the lateral conductivity of the dissipator. In another embodiment, the rear face of the dissipator is not flush with the outer upper face 56, but buried under a thin blade of the thick layer 54. Typically, the thickness of this thick layer blade is less than 50 μm, and preferably less than 10 μm or 5 μm. The front face of the dissipator can be fixed on the rear face of the electronic chip by other means. For example, alternatively, the pads 44 and 66 are omitted and the front face is fixed on the back side only by means of an adhesive, such as glue 68. In this case, the front face is not directly mechanical contact with the back side of the electronic chip. The thermally conductive particles mixed with the gluing materials in the glue 68 may be omitted. Similarly, the glues provided under the chip 26 and under the dissipator may be different. For example, the glue dispensed only under the chip 26 has a lower thermal conductivity than that provided under the dissipator. In the case where the heat sink is mechanically and thermally fixed on the chip 24 by pads, the adhesive dispensed between these pots can be omitted. [0097] Other cooling systems of the upper outer face of the integrated circuit are possible. For example, it is possible to use a fluidic cooling system comprising channels which bring a heat-transfer liquid in direct contact with the face 56 and channels which evacuate this heat-transfer liquid after it has been heated by thermal conduction with this face 56. Alternatively, the step of removing the residual layer 170 between the pads 44 is omitted.
    权利要求:
    Claims (11)
    [0001]
    REVENDICATIONS1. An integrated circuit comprising: a substrate (10) which extends mainly in a plane called a "plane of the substrate", said substrate being provided with electrical connections for electrically connecting the integrated circuit to an external electronic circuit, said substrate having a face interior (20), - a high electronic chip (22, 26) and a low chip (24; 220), each of these electronic chips being electrically connected to the electrical connections via this substrate and each electronic chip comprising a front face facing the inner face of the substrate and a rear face of the opposite side to this front face, the rear face (32) of the high electronic chip being located at a height H above the inner face (20) of the substrate and being further away from the inner face (20) of the substrate than the rear face (36) of the low electronic chip, - a housing formed by a couch e thick (54) of electrically insulating material which encapsulates the electronic chips, this thick layer forming an upper outer surface (56) of the housing parallel to the plane of the substrate 'characterized in that the integrated circuit comprises a dissipator (60; 150; 222) of heat without electronic components and interposed between the rear face (36) of the low chip and the upper outer face (56) of the housing, said sink having a front face (62; 152) disposed on the back side of the low chip and a rear face (64) on the opposite side to the front face, this rear face being between first and second planes parallel to the plane of the substrate, the first and second planes being respectively located, at 0.15 * H below and 0.15 * H above the rear face of the high chip, the thermal conductivity at 25 ° C of the sink in a direction perpendicular to the plane of the substrate being at least two times greater than the thermal conductivity of the thick layer measured under the same conditions and in the same direction. 30
    [0002]
    2. Integrated circuit according to claim 1, wherein: the front face (30, 38) of the high electronic chip comprises studs (42, 44), these studs being directly mechanically and electrically connected to studs (44) in FIG. with a view to transmitting electrical signals between the high electronic chip and an electronic circuit (8) external to this high electronic chip via these pads, - the rear face (36) of the electronic chip base comprises studs (44), - the front face (62) of the dissipator comprises studs (66) mechanically fixed on the studs (44) vis-à-vis the rear face of the low chip of the same man- the pads (42, 44) of the high electronic chip are fixed on pads facing each other.
    [0003]
    3. Circuit according to claim 1, wherein the rear face (36) of the low chip comprises an electrically insulating flat layer (166) for electrically isolating this low electronic chip from the external environment, and the front face (152). the dissipator is flat and directly in mechanical contact on this flat layer of the rear face of the low chip.
    [0004]
    4. Circuit according to any one of the preceding claims, wherein the portion of the front face (62; 152) of the dissipator directly in mechanical contact with the rear face (36) of the low chip occupies at least 10% or 30%. % of the area of the orthogonal projection of the rear face of the low chip on the substrate plane.
    [0005]
    5. Circuit according to claim 4, wherein the surface of the orthogonal projection of the front face of the dissipator (222) on the plane of the substrate is at least 1.1 times greater than the area of the orthogonal projection of the rear face of the low chip (220) on the same plane.
    [0006]
    6. Circuit according to any one of the preceding claims, wherein the heat capacity of the heat sink is less than 1200 J / Kg / K or 1000 J / Kg / K under normal conditions of temperature and pressure.
    [0007]
    7. Circuit according to any one of the preceding claims, wherein the thickness of the dissipator in a direction perpendicular to the plane of the substrate is greater than 70 pm.
    [0008]
    8. Circuit according to any one of the preceding claims, wherein the rear face (32, 40) of the high electronic chip and the rear face (64) of the dissipator are flush with the upper outer face of the housing.
    [0009]
    9. An assembly comprising: an integrated circuit (4; 148; 218) having an upper outer face, and a radiator (70) or a fluidic cooling system using a coolant for cooling the upper outer face of the integrated circuit, the radiator or the fluidic cooling system being directly disposed on the upper outer face of this integrated circuit, characterized in that the integrated circuit is according to any one of the preceding claims.
    [0010]
    10. A method of manufacturing an integrated circuit according to any one of claims 1 to 8, characterized in that the method comprises the realization (182, 188, 190, 192, 194, 200, 202, 204) of the dissipator of heat interposed between the rear face of the low chip and the upper outer face of the housing.
    [0011]
    11. The method of claim 10, wherein the realization of the dissipator 10 comprises the growth (188) by electrolysis, on the rear face of the low chip, a layer of a material whose thermal conductivity is at least two times greater than the thermal conductivity of the thick layer when measured under the same conditions and in the same direction, this growth by electrolysis being interrupted at the moment when the thickness of this layer is such that, after the assembly of the high electronic chip on the integrated circuit substrate, the rear face of the dissipator is between a first and a second plane parallel to the plane of the substrate, the first and second planes being respectively 0.15 * H below and at 0.15 * H above the back side of the high chip. The method of claim 10 or 11, wherein the dissipator is carried (118) on the back side of the low chip by gluing or by means of pads. A method according to claim 12, characterized in that when the dissipator is carried on the rear face of the low chip and attached to the low chip by pins, the method comprises a step (124) for filling the chip. space created by the pads by an adhesive containing thermally conductive particles.
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    同族专利:
    公开号 | 公开日
    EP2960937A3|2016-01-06|
    US20150380387A1|2015-12-31|
    US9240394B1|2016-01-19|
    EP2960937A2|2015-12-30|
    EP2960937B1|2018-05-16|
    FR3023059B1|2018-01-05|
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    法律状态:
    2015-06-30| PLFP| Fee payment|Year of fee payment: 2 |
    2016-01-01| PLSC| Search report ready|Effective date: 20160101 |
    2016-07-08| PLFP| Fee payment|Year of fee payment: 3 |
    2017-06-30| PLFP| Fee payment|Year of fee payment: 4 |
    2018-06-27| PLFP| Fee payment|Year of fee payment: 5 |
    2020-03-13| ST| Notification of lapse|Effective date: 20200206 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1455936|2014-06-25|
    FR1455936A|FR3023059B1|2014-06-25|2014-06-25|INTEGRATED CIRCUIT COMPRISING A HEAT SINK|FR1455936A| FR3023059B1|2014-06-25|2014-06-25|INTEGRATED CIRCUIT COMPRISING A HEAT SINK|
    US14/747,136| US9240394B1|2014-06-25|2015-06-23|Stacked chips attached to heat sink having bonding pads|
    EP15173470.4A| EP2960937B1|2014-06-25|2015-06-23|Integrated circuit comprising a heat sink|
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